The power supply on a logic chip must accommodate variations in current draw from different parts of the on-chip circuit. Typically, there is a time lag between the changes in voltage within the circuit before the power supply responds. This requirement can be met by having an on-chip metal—insulator—metal (MIM) capacitor, consisting of a high-k dielectric layer formed between bottom and top electrodes. The capacitor can be used to provide a steady source of current during the response time of the power supply. The requirements for this high-k dielectric include providing sufficient capacitance or equivalent oxide thickness (EOT) (e.g. relative to silicon dioxide) to meet the requirements for charge storage, and having sufficiently low leakage to allow charge to be stored for at least 1 ms. Furthermore, the high-k dielectric should be able to operate reliably at typical sense voltages (˜1.0V) for the lifetime of the product (e.g. typically >10 years). Finally, the high-k dielectric should have a low defect density (e.g. pinhole defects or grain boundaries) which can be a source of leakage or charge loss in these capacitors. The defect density places an upper limit on the size of the capacitor that can be used in a chip. In some cases, the capacitor is divided into smaller capacitors which are connected in parallel to minimize the occurrence of these pinhole or grain boundary defects.
There is a need to develop dielectric materials and MIM capacitor stacks that meet these requirements as decoupling capacitors for advanced and future logic circuits.